About the role
Remote contract for digital hardware engineers: turn real RTL work into design, bug-fix and PPA (power, performance, area) tasks for AI models, with specification, starting design, reference solution and tests, graded with real simulation, synthesis and equivalence-checking flows. About 2 months, minimum 40 hours a week with 4 hours' overlap with U.S. Pacific time.
Experience
BS/MS in electrical, electronic or computer engineering or equivalent; 3+ years of front-end ASIC or FPGA design; fluent Verilog/SystemVerilog; hands-on synthesis (Genus, Design Compiler, Vivado) and open-source EDA (Yosys, Verilator, cocotb); Python and Tcl.
Selection process
Apply through the official Turing page (free account required). The listing mentions an assessment-based evaluation.
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Eligibility
Not stated on the listing (remote)